Verilog HDL code

HDL code for Not gate:
module not_gates (input a, b, output d);
not (d, a, b);  // d is the output, a and b are inputs
endmodule 

HDL code for AND gate:
module and_gate (a, b, y);
input a, b;
output y;
assign y = a & b;
endmodule 

Test bench for AND gate:

module and_gate_tb;
wire t_y;
reg t_a, t_b;
and_gate my_gate( .a(t_a), .b(t_b), .y(t_y) );
initial
begin
$monitor(t_a, t_b, t_y);
t_a = 1'b0;
t_b = 1'b0;
#4
t_a = 1'b0;
t_b = 1'b1;
#3
t_a = 1'b1;
t_b = 1'b0;
#5
t_a = 1'b1;
t_b = 1'b1;
end
endmodule