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VLSI Verification Code Tutorial

VLSI Verification is a Front-End approach for both FPGA and ASIC design, it is consisting of Methodologies and languages. Verification is simply process of checking the design correctness and achieve its goal without any Bugs. This blog is created to share contents on one platform. 1]VLSI Tutorial 2]Verilog 3]System Verilog 4]Perl 5]C/OOP

PERL CODE

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October 24, 2020

Perl is a programming language developed by L. Wall especially designed for text processing. It is known as Practical Extraction and Report langauge.

PERL

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VLSI Verification basic

October 17, 2020

What is Verification? how it is differ from testing (Validation). Verification of VLSI design(FPGA or ASIC) is to check the correctness of design. Method like simulation, hardware emulation and formal checking, it is performed before manufacturing the product and hence responsible for quality of design. Verification focuses on finding functional bugs and fix it using test-bench, there are different type of verification like IP Verification, RTL Verification , Timing Verification etc. Testing is use to check the correctness of Manufactured hardware design, it is like fault or defect testing, Functional testing. Mostly it is check by using electrical test cases or both Software and Hardware together. Difference between ASIC and FPGA design? and its design flow. ASIC: An integrated circuit customized for particular use rather than for general purpose tasks. FPGA: An integrated circuit designed to be configured by customer or designer after manufac...

Eligibility criteria for VLSI Verification Engineer

October 24, 2020

Eligibility criteria for VLSI Verification Engineer? Frontend Verification Engineer:--FPGA or ASIC Engineer. Languages: Verilog, System Verilog, Perl, C, PERL Tools: XILINX ISE, XILINX Vivado, NCSIM, ModelSim, VCS. Protocols: AMBA, PCIE, I2C

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K_Bhosale: A blog is created to share the knowledge of VLSI, Which includes VLSI tech. , Verilog, System Verilog, Perl and question paper series.

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