VLSI Verification basic

 What is Verification? how it is differ from testing (Validation).

Verification of VLSI design(FPGA or ASIC) is to check the correctness of design. Method like simulation, hardware emulation and formal checking, it is performed before manufacturing the product and hence responsible for quality of design.

Verification focuses on finding functional bugs and fix it using test-bench, there are different type of verification like IP Verification, RTL Verification , Timing Verification etc.  

Testing is use to check the correctness of Manufactured hardware design, it is like fault or defect testing, Functional testing. Mostly it is check by using electrical test cases or both Software and Hardware together.  

Difference between ASIC and FPGA design? and its design flow.

ASIC: An integrated circuit customized for particular use rather than for general purpose tasks.

FPGA: An integrated circuit designed to be configured by customer or designer after manufacturing.

 

Standard cell ASIC’s (Application Specific Integrated Ckt.)/CBIC	FPGA(Field Programmable Gate Arrays)
It is a Semi custom ASIC design with non programmable feature.	It is also semi custom ASIC design with Programmable feature.
Standard cell are predefined in library Cell base. ASIC is designed by using multiplexer, gates, flip flop it is also knows as logic cell.	Programmable I/O cell, FPGA is design by using mux, gates, flip flop etc.
Due to Complexity Mask cost, Development cost is High.	FPGA offer good option to reduce re-spine, cost and delays.
Additional Delay occurs due to Power, Signal Integrity, Synthesis and manufacturing defects.	FPGA synthesis much easier than ASIC
The higher frequency can be achieved on the node	Small operating is achieved on the node.
The power consumption is less as compared to FPGA	The power consumption is Higher than ASIC
ASIC suited for bulk production	FPGA doesn’t suited bulk production

             

 

What is Verilog HDL?

Verilog Hardware description Language for describing Electronics circuits, and it is use in programming logical design. This is different from software programming language because HDL includes propagation delay and signal timings. Both structural and behavioral statements use, structural statement signify logical components likes gates, counter etc. Whereas in behavioral statements consist of loops likes if-else, do etc.

e.g.

timing constraints:

"timescale 1ns/2ps" //signify Accuracy/Precision;

module Ver(Y,A);

output Y;

input A;

assign Y=~A;

endmodule

What is System Verilog?

System Verilog is Hardware description and Verification language, it is also known as HDVL. Because it has combinational feature of Verilog and Object Oriented Programming language.

Practical application in coding is to Assertion, Randomization, functional coding Coverage driven etc.

System verilog first became official IEEE in 2005.

E.g.

// Design D flip-flop

module Dff (clk1, reset,

  d, q, qb);

  input      clk1;

  input      reset;

  input      d;

  output     q;     //Output

  output     qb;   // Output

  reg        q;       //Store

  assign qb = ~q;

  always @(posedge clk1 or posedge reset)

  begin

    if (reset) begin // Asynchronous reset when reset goes high

      q <= 1'b0;

    end else begin // Assign D to Q on positive clock edge

      q <= d;

    end

  end

endmodule