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Verilog HDL code

HDL code for Not gate: module not_gates (input a, b, output d); not (d, a, b);  // d is the output, a and b are inputs endmodule   HDL code for AND gate: module and_gate (a, b, y); input a, b; output y; assign y = a & b; endmodule   Test bench for AND gate: module and_gate_tb; wire t_y; reg t_a, t_b; and_gate my_gate( .a(t_a), .b(t_b), .y(t_y) ); initial begin $monitor(t_a, t_b, t_y); t_a = 1'b0; t_b = 1'b0; #4 t_a = 1'b0; t_b = 1'b1; #3 t_a = 1'b1; t_b = 1'b0; #5 t_a = 1'b1; t_b = 1'b1; end endmodule
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PERL CODE

 Perl is a programming language developed by L. Wall especially designed for text processing. It is known as Practical Extraction and Report langauge. 
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Eligibility criteria for VLSI Verification Engineer

 Eligibility criteria for VLSI Verification Engineer? Frontend Verification Engineer:--FPGA or ASIC Engineer. Languages: Verilog, System Verilog, Perl, C, PERL Tools: XILINX ISE, XILINX Vivado, NCSIM, ModelSim, VCS.  Protocols: AMBA, PCIE, I2C
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VLSI Verification basic

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  What is Verification? how it is differ from testing (Validation). Verification of VLSI design(FPGA or ASIC) is to check the correctness of design. Method like simulation, hardware emulation and formal checking, it is performed before manufacturing the product and hence responsible for quality of design. Verification focuses on finding functional bugs and fix it using test-bench, there are different type of verification like IP Verification, RTL Verification , Timing Verification etc.   Testing is use to check the correctness of Manufactured hardware design, it is like fault or defect testing, Functional testing. Mostly it is check by using electrical test cases or both Software and Hardware together.   Difference between ASIC and FPGA design? and its design flow. ASIC: An integrated circuit customized for particular use rather than for general purpose tasks. FPGA: An integrated circuit designed to be configured by customer or designer after manufac...
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